The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
As the geometry sizes shrink, it may be difficult for conventional photolithography processes to form semiconductor features having these small geometry sizes. A double patterning technology method may be used to form the semiconductor features having small geometry sizes. Double patterning methods usually involve a pattern decomposition process, which can be performed at a design stage or at a fabrication stage. However, if the decomposition process is performed at the design stage, the decomposition process may ignore fabrication issues such as load balancing, and thus lead to sub-optimal fabrication results. On the other hand, if the decomposition is performed at the fabrication stage, the decomposition process may not be able to fully address design concerns such as critical path mismatches due to double patterning.
Therefore, while existing double patterning methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.